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Browse Prior Art Database

PRF Signal Analyzer

IP.com Disclosure Number: IPCOM000091695D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 4 page(s) / 60K

Publishing Venue

IBM

Related People

Bates, JK: AUTHOR

Abstract

The system of A analyzes the pulse repetition frequency PRF of a recurring input signal. The system has one or more logic stages I, II and III, etc. Each stage analyzes signals within a predetermined periodicity range. In the analog arrangement of A, the succeeding stages analyze successive octave, 2:1 signal frequency groupings. Thus, for example, stage I provides discrete output terminals 3.5T, 4.0T...6.0T for signals having respective corresponding periodicities of 3.5T, 4.0T...6.0T. Stage II provides discrete output terminals 7T, 8T...12T for signals having respective corresponding periodicities of 7T, 8T...12T, etc. The system can be arranged to provide additional terminals in each stage in order to obtain either greater resolution or expanded ranges or both.

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PRF Signal Analyzer

The system of A analyzes the pulse repetition frequency PRF of a recurring input signal. The system has one or more logic stages I, II and III, etc. Each stage analyzes signals within a predetermined periodicity range. In the analog arrangement of A, the succeeding stages analyze successive octave, 2:1 signal frequency groupings. Thus, for example, stage I provides discrete output terminals 3.5T, 4.0T...6.0T for signals having respective corresponding periodicities of 3.5T, 4.0T...6.0T. Stage II provides discrete output terminals 7T, 8T...12T for signals having respective corresponding periodicities of 7T, 8T...12T, etc. The system can be arranged to provide additional terminals in each stage in order to obtain either greater resolution or expanded ranges or both.

The signal to be analyzed is applied to input terminal Ein. Filter 20 has a bandpass characteristic compatible to that for which the system is devised. Signal converter 21, in response to the filtered input signal, converts it to an output pulse train with a resultant corresponding periodicity. Each pulse of converter 21 has a predetermined pulsewidth t1 which is less than the unit time period T. The pulses of converter 21 interrogate each of the logic stages at input terminals Interrogate. The output of converter 21 is also connected to the input of converter 22 which provides a second pulse train having the same pulse repetition frequency. The pulses of the second train have a pulsewidth t2 which is substantially less than pulsewidth t1. After a time delay t3 = t1 - t2 provided by delay 23, the pulses so delayed are fed to input terminals Propagate of the logic stages.

Signals appearing at terminals 1st, 2nd, etc., coact with the Or 24 and Inverter 25 to provide inhibit signals to the respective input terminals Inhibit. Each stage is also provided with an input terminal Sync which is connected to the output of Or 24 and simultaneously conditions the And's, e.g., And's 41...46 of stage I, connected to the Output terminals of the particular stage.

Only elements 31...50 of stage I are shown in detail at A. Stages II, III, etc., have corresponding and similarly arranged elements. The only difference between stages is the incremental delay time periods 4 Delay provided between each of the taps of a delay device which is included in each stage, e.g., delay line 50 of stage I. In stage I, delay line 50 has a delta Delay = 20T = T between each of its successive taps 0, 1, 2...12. In stage II, the delta Delay = 2/1/T- in stage All, the delta Delay = 2/2/T = 4T; and for the last stage N the delta Delay = 2/(N- 1)/T. Moreover, each single-shot included in each stage, e.g., multivibrator 49 of stage I, when triggered, generates a pulse having a width corresponding to the delta Delay of the delay line, e.g., delay line 50, to which it is connected at the input terminal, e.g., terminal 0.

Initially, when the system is placed in operation, there are no pulses bein...