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Monitoring Error Correcting Circuits

IP.com Disclosure Number: IPCOM000091707D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Williams, C: AUTHOR [+3]

Abstract

In a storage system where high availability is a feature, error checking and correcting circuits ECC are provided to detect errors in data being delivered from the store and to correct errors in certain specified classes. When monitoring the correct functioning of the error-correcting circuits, it is desirable to avoid introducing more hardware because of the possibility of errors occurring in that hardware.

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Monitoring Error Correcting Circuits

In a storage system where high availability is a feature, error checking and correcting circuits ECC are provided to detect errors in data being delivered from the store and to correct errors in certain specified classes. When monitoring the correct functioning of the error-correcting circuits, it is desirable to avoid introducing more hardware because of the possibility of errors occurring in that hardware.

Store 1 is arranged to receive data in the form of 64-bit words over input bus
2. Eight parity bits are added to each data word, as it is entered, by a parity generator 3. The bits are chosen in accordance with a specified code to make provision for detection and correction of certain specified errors. When a word is recovered from the store over output bus 4, parity bits are developed from it in accordance with the code and are compared with the bits that are stored with the word. If agreement is obtained, no error has occurred in the storage operation. If there is disagreement, an error has occurred, the location of which and the nature of which, i.e., whether correctable or incorrectable, is described by the result of the comparison.

In order to make provision for monitoring the correct functioning of the arrangement, a manual or program-controlled entry device 5 is provided in the loop between bus 2 and bus 4. When this entry device is operative, it permits individual bits in a word applied to the store to be changed w...