Browse Prior Art Database

Integrated Circuits

IP.com Disclosure Number: IPCOM000091710D
Original Publication Date: 1968-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Heneghan, MJ: AUTHOR

Abstract

Emitter resistors R1...R3 of output transistors T1...T3 for circuits 22...24 on chip 21 can be isolated by reverse-biasing diodes S1...S3 by applying appropriate bias potential to terminal 28. The emitters of T1...T3 are respectively connected to output terminals 26, 29, and 30. The arrangement enables connection of terminals 26, 29, and 30 to either long transmission lines, in which case R1...R3 are isolated, or to short transmission lines, in which case S1...S3 are forward-biased by the potential on terminal 28 and the output transistors act as emitter-followers. Dot-Oring of terminals 26, 29, and 30 on several chips made possible by isolating R1...R3 of all chips except one. For flexibility, the resistors can be connected in groups, each group to a different terminal such as 28.

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Integrated Circuits

Emitter resistors R1...R3 of output transistors T1...T3 for circuits 22...24 on chip 21 can be isolated by reverse-biasing diodes S1...S3 by applying appropriate bias potential to terminal 28.

The emitters of T1...T3 are respectively connected to output terminals 26, 29, and 30. The arrangement enables connection of terminals 26, 29, and 30 to either long transmission lines, in which case R1...R3 are isolated, or to short transmission lines, in which case S1...S3 are forward-biased by the potential on terminal 28 and the output transistors act as emitter-followers. Dot-Oring of terminals 26, 29, and 30 on several chips made possible by isolating R1...R3 of all chips except one. For flexibility, the resistors can be connected in groups, each group to a different terminal such as
28. The diodes can be replaced by transistors and the bias applied to the transistor bases.

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