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Low Power Monolithic Memory Cell

IP.com Disclosure Number: IPCOM000091723D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Furman, A: AUTHOR

Abstract

A four-layer diode or PNPN hook can be used as a bistable element in a storage cell where it operates at very low-power levels. Transistors Q1 and Q2 are the transistor equivalent of a four-layer PNPN diode. This diode is considered to be in the 1 state when Q1 and Q2 are conducting and in the 0 state when they are off. If the latch is in the 1 state, the base of transistor Q3 is higher than the base of Q4. The state of Q1 and Q2 is interrogated by the application of a read pulse to the emitters of Q3 and Q4. Therefore Q3 conducts when the cell is interrogated by a read pulse. This generates a voltage across output resistor R1. If the cell is off or in the 0 state when the read pulse is applied to the emitters of Q3 and Q4, the base of Q4 is higher than the base of Q3.

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Low Power Monolithic Memory Cell

A four-layer diode or PNPN hook can be used as a bistable element in a storage cell where it operates at very low-power levels.

Transistors Q1 and Q2 are the transistor equivalent of a four-layer PNPN diode. This diode is considered to be in the 1 state when Q1 and Q2 are conducting and in the 0 state when they are off. If the latch is in the 1 state, the base of transistor Q3 is higher than the base of Q4. The state of Q1 and Q2 is interrogated by the application of a read pulse to the emitters of Q3 and Q4. Therefore Q3 conducts when the cell is interrogated by a read pulse. This generates a voltage across output resistor R1. If the cell is off or in the 0 state when the read pulse is applied to the emitters of Q3 and Q4, the base of Q4 is higher than the base of Q3. Therefore, Q4 conducts so that there is no current drawn through R1.

All the cells in a word line are reset to the 0 state by the application of a positive pulse to the anode of diode D3. This back biases the base-to-emitter junction of Q1 thus turning Q1 and Q2 off. To then write a 1 in the cell, bit driver transistor Q5 is turned on and at the same time a read pulse is applied to the emitter of Q3 and Q4. Since the cell has been reset to the 0 state, the base of Q4 is higher than the base of Q3 so that Q4 turns on. Since diode D1 is back biased by the conducting bit driver Q5, the collector current for Q4 comes from D2 turning on Q1 and Q2.

Characteristics of the...