Browse Prior Art Database

FET Inverter

IP.com Disclosure Number: IPCOM000091724D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Pomeranz, JN: AUTHOR [+3]

Abstract

This FET inverter has low-power dissipation yet a relatively low-output impedance so as to make it suitable to drive capacitive loads. Capacitor CL is initially charged to some negative potential. At some time T, input pulse A is applied to the gate of FET T2. This causes CL to discharge through T2 towards ground. At some later time, a negative potential is applied to the gate of FET T1 causing it to conduct and charge CL to a negative potential. With this circuit, rapid transitions of A can be achieved by making Absolute value V(A)> absolute value V (of T2) absolute value +-V + absolute value V (of T1).

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FET Inverter

This FET inverter has low-power dissipation yet a relatively low-output impedance so as to make it suitable to drive capacitive loads. Capacitor CL is initially charged to some negative potential. At some time T, input pulse A is applied to the gate of FET T2. This causes CL to discharge through T2 towards ground. At some later time, a negative potential is applied to the gate of FET T1 causing it to conduct and charge CL to a negative potential. With this circuit, rapid transitions of A can be achieved by making Absolute value V(A)> absolute value V (of T2) absolute value +-V + absolute value V (of T1).

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