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Null Zone Digital Matched Filter

IP.com Disclosure Number: IPCOM000091735D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Roehr, WC: AUTHOR

Abstract

A digital-matched filter with greatly reduced error rates is realized by the combination of dual-threshold device 10 and shift registers 20. A single two-stage null zone, digital-matched filter DMF. Device 10 recognizes not only 1's and 0's but also don't care values. The device 10 1 output is high whenever the input signal is clearly high, causing a Set condition in T1. The 0 output is high whenever the input is clearly low causing a Set condition in register T3. A Set condition in neither shift register results from a null zone, i.e., don't care condition. The state of the two input shift register stages is shifted down the register synchronously at the received bit rate.

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Null Zone Digital Matched Filter

A digital-matched filter with greatly reduced error rates is realized by the combination of dual-threshold device 10 and shift registers 20. A single two-stage null zone, digital-matched filter DMF. Device 10 recognizes not only 1's and 0's but also don't care values. The device 10 1 output is high whenever the input signal is clearly high, causing a Set condition in T1. The 0 output is high whenever the input is clearly low causing a Set condition in register T3. A Set condition in neither shift register results from a null zone, i.e., don't care condition. The state of the two input shift register stages is shifted down the register synchronously at the received bit rate.

The connection of summing resistors R1...R4 is a function of the expected word. Separate banks of similar resistors are connected to the shift registers if more than one word is expected. The number of shift register stages can also be increased in order to accommodate longer words. The drawing shows a DMF for a two-bit word 01. The order of digits is reversed in the shift register.

The expression for the output voltage is (nVRs+BR)/>Rs(n+w)+R|. V is the high voltage of a shift register stage, n is the number of correct stages, and w equals the number of incorrect stages. Rs is the summing resistor R5. R equals resistor R1 or R2 or R3 or R4. B is the bias voltage.

For example, assume that the first received bit is a 0, correctly shifted into T2 and T4, while...