Browse Prior Art Database

Low Ripple Latch Clock

IP.com Disclosure Number: IPCOM000091748D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Johnson, DW: AUTHOR

Abstract

The latch clock combines the relative simplicity of a ripple counter with some of the speed of a nonripple counter. No additional latches are required, but at any timing pulse only one stage changes state. The waveforms show pulse sequences TA and TB that are the stepping inputs to the four latch stages A...D. These stages count in the sequence shown by the waveforms. If more than four counts are required, two or more sets of four latches can be cascaded. The inputs to the next four latches, as an example, analogous to TA and TB, are TA' = Clock Latch AA, Not Clock Latch C, and TB' = Clock Latch D.

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Low Ripple Latch Clock

The latch clock combines the relative simplicity of a ripple counter with some of the speed of a nonripple counter. No additional latches are required, but at any timing pulse only one stage changes state. The waveforms show pulse sequences TA and TB that are the stepping inputs to the four latch stages A...D. These stages count in the sequence shown by the waveforms. If more than four counts are required, two or more sets of four latches can be cascaded. The inputs to the next four latches, as an example, analogous to TA and TB, are TA' = Clock Latch AA, Not Clock Latch C, and TB' = Clock Latch D.

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