Browse Prior Art Database

Latch Counter

IP.com Disclosure Number: IPCOM000091749D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Johnson, DW: AUTHOR

Abstract

The latch counter incorporates single latches in certain stages that share a common storage latch. Thus, less hardware is required when contrasted with a conventional latch counter that normally requires a latch pair for each stage. Stages B3, B2, and B1 are single latches. Stages A2 and A1 are latch pairs. Since only one stages B3, B2, or B1 changes state from one count to the next, these stages share a common storage, steering, latch 1. Stages A2 and A1 operate as a straight binary counter.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 89% of the total text.

Page 1 of 2

Latch Counter

The latch counter incorporates single latches in certain stages that share a common storage latch. Thus, less hardware is required when contrasted with a conventional latch counter that normally requires a latch pair for each stage. Stages B3, B2, and B1 are single latches. Stages A2 and A1 are latch pairs. Since only one stages B3, B2, or B1 changes state from one count to the next, these stages share a common storage, steering, latch 1. Stages A2 and A1 operate as a straight binary counter.

Control 2 supplies timing pulses T1...T4. Gates G1, G2, and G3 determine which B stage is steered by latch 1 during each step and are controlled by the A stages at terminals 3, 4, and 5 at time T1 to gate latch 1. At time T2, add gate 6 sets the B latches through gates S1, S2, and S3 under control of latch 1 and carry latch 7 which is set by A1A2 = 00 or by adding a 1 to a B latch on the previous step that was already at a 1 condition. When the B stages assume their proper states the A stages are advanced at T3 time. Latch 1 is reset at T4 time.

The count pattern is as below with the order of bits, from left, B3, B2, B1, A2 and A1. 1. 0 0 0 0 0 9. 0 1 0 0 0 17. 1 0 0 0 0 25. 1 1 0 0 0 2. 0 0 1 0 1 10. 0 1 1 0 1 18. 1 0 1 0 1 26. 1 1 1 0 1 3. 0 0 1 1 0 11. 0 1 1 1 0 19. 1 0 1 1 0
27. 1 1 1 1 0 4. 0 0 1 1 1 12. 0 1 1 1 1 20. 1 0 1 1 1 28. 1 1 1 1 1 5. 0 0 1 0 0 13. 0 1 1 0 0 21. 1 0 1 0 0 29. 1 1 1 0 0 6. 0 0 0 0 1 14. 0 1 0 0 1 22. 1 0 0 0 1 30. 1 1 0 0 1 7. 0 1...