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Two Level Storage Hierarchy With Error Correcting

IP.com Disclosure Number: IPCOM000091792D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Craft, JL: AUTHOR

Abstract

The storage system includes drum stores D and magnetic memory units M which are interconnected by data registers DR. The system possesses repairable redundancy, that is, sufficient redundancy to enable error correction after certain types of errors occur so that system failure is avoided. The system configuration, which inherently has large storage capacity, provides a long mean time between failure. The system includes a plurality of magnetic drums D1...D(n+x). Drums D are normally operated in synchronization although each drum can be independently powered. If so, the drums are mechanically independent of each other. Data is read into and out of the drums through respective register and gating circuits RC. Circuits RG1...RG(n+x) are identical, the details of which are shown in circuit RGn.

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Two Level Storage Hierarchy With Error Correcting

The storage system includes drum stores D and magnetic memory units M which are interconnected by data registers DR. The system possesses repairable redundancy, that is, sufficient redundancy to enable error correction after certain types of errors occur so that system failure is avoided. The system configuration, which inherently has large storage capacity, provides a long mean time between failure. The system includes a plurality of magnetic drums D1...D(n+x). Drums D are normally operated in synchronization although each drum can be independently powered. If so, the drums are mechanically independent of each other. Data is read into and out of the drums through respective register and gating circuits RC. Circuits RG1...RG(n+x) are identical, the details of which are shown in circuit RGn.

With reference to RGn, data is read from Dn through input gates I to DRn. From DRn, data is read to memory Mn. Data is returned to DRn from Mn after which that data may be returned to Dn via output gates 0. The contents of the DR's are all supplied to an error-checking and correcting circuit ECC which checks and corrects the information in the DR's. The ECC circuitry can be supplied via gates I and O rather than from the DR's as shown. Data is organized in the system on the basis of either a bit-per-drum or a bit-per-memory unit. With data organized into eight-bit bytes, n is equal to eight and a bit of each eight-bit byte is stored respectively in either D1...D8 or in M1...M8 or both. In addition to the eight data bits, error-correcting or redundancy bits are also included with each byte. For example, using a single error-correcting Hamming code, four additional bits are distributed over either D(8+1)...D(8+4) or M(8+1)...M(8+4) or both.

With data organized as described, error checking and correcting is carried out in ECC by simultaneously gating all the data bits and all the redundancy bits for a single byte to ECC. If an error is detected, it is corrected in the Hamming error-correcting manner before information in a DR is transferred out to either the drums or the memory units. Since, in normal operation, the drums are operating in synchronization, common gating circuitry, not shown, can be employed to gate a byte, including a bit from each circuit RG1...RG(n+x), to ECC. For example, at a first time, a common signal to all RG's on lines GIO is used to gate the 0 bit from each DR to ECC. Similarly during a second time, a common gating signal ...