Browse Prior Art Database

Pulse Generating System

IP.com Disclosure Number: IPCOM000091798D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Ligon, GC: AUTHOR

Abstract

The clock is for supplying accurately timed pulses to operate a memory through a read and write cycle. The read and write pulses are applied to a set of drivers, selected according to an address that is supplied to the memory. The read and write pulses are identical in rise time, fall time, and pulse duration, but they are generated at different times in the clock cycle. The start read pulse and the start write pulse are provided by a tapped delay line and are applied to the input of an Or. The latter is connected with an And, a delay, and an Inverter 1 to form a monostable circuit. The latter produces a pulse of the desired shape in response to either a read or write input pulse. In response to an input from either the read or write tap on the delay line, the Or produces an input to the And.

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Pulse Generating System

The clock is for supplying accurately timed pulses to operate a memory through a read and write cycle. The read and write pulses are applied to a set of drivers, selected according to an address that is supplied to the memory. The read and write pulses are identical in rise time, fall time, and pulse duration, but they are generated at different times in the clock cycle. The start read pulse and the start write pulse are provided by a tapped delay line and are applied to the input of an Or. The latter is connected with an And, a delay, and an Inverter 1 to form a monostable circuit. The latter produces a pulse of the desired shape in response to either a read or write input pulse. In response to an input from either the read or write tap on the delay line, the Or produces an input to the And. The latter, in turn, produces an output that is applied to a memory driver and is also applied as an input to the Or. This input to the Or maintains such Or on without regard to the status of the inputs from the tapped delay line. The delay and I cooperate to turn off the And and thus terminate the read and write pulses after a time interval that is established by the delay circuit.

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