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Browse Prior Art Database

Variable Frequency Sequential Address Generator

IP.com Disclosure Number: IPCOM000091801D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Gifford, CE: AUTHOR [+2]

Abstract

Memories are often tested by performing a standard operation at each memory address in succession. In this circuit, two counters 3 and 4 are driven from common oscillator 5 to provide a sequence of addresses for memory address register 6. An even input line 7 and an odd input line 8 are alternately energized to operate counters 3 and 4 in an interleaved mode. With this arrangement, slow-speed counters provide addresses at the higher rate required for testing the memory.

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Variable Frequency Sequential Address Generator

Memories are often tested by performing a standard operation at each memory address in succession. In this circuit, two counters 3 and 4 are driven from common oscillator 5 to provide a sequence of addresses for memory address register 6. An even input line 7 and an odd input line 8 are alternately energized to operate counters 3 and 4 in an interleaved mode. With this arrangement, slow-speed counters provide addresses at the higher rate required for testing the memory.

This address generator operates at several different frequencies. It takes advantage of the fact that each counter stage operates at twice the frequency of the next higher order stage. The logic circuits associated with bit positions 0...3 of the counter are controlled according to three input lines to establish the frequency of the address generator. At the highest frequency, line F is energized to control bit position 0 of register 6 to receive pulses from the 0 bit positions of the counters.

At the next highest frequency, line F/2 is energized to control bit position 0 of register 6 to receive pulses from bit position 1 of the counters. When the circuit is operating at frequency F/2, the 0 bit positions of the counter do not provide pulses to register 6 but act as frequency dividers for pulses transmitted from oscillator 5 to succeeding stages of the counters. The operation at the lower frequency F/4 and the operation at address bit position 1 of...