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Clock Synchronization

IP.com Disclosure Number: IPCOM000091818D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Fiorino, BC: AUTHOR [+2]

Abstract

Clock synchronization is obtained from a series of constant frequency sync pulses. These precede irregularly occurring data pulses by running the clock at the sync pulse frequency until synchronization is effected and then switching the clock to the maximum data frequency. In addition, the time constant of the memory controlling the clock is switched between a fast response mode for facilitating synchronization and a slow response mode for data detection operation. The system is useful for controlling the common variable frequency clock used in frequency encoded and modified frequency encoded magnetic tape systems.

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Clock Synchronization

Clock synchronization is obtained from a series of constant frequency sync pulses. These precede irregularly occurring data pulses by running the clock at the sync pulse frequency until synchronization is effected and then switching the clock to the maximum data frequency. In addition, the time constant of the memory controlling the clock is switched between a fast response mode for facilitating synchronization and a slow response mode for data detection operation. The system is useful for controlling the common variable frequency clock used in frequency encoded and modified frequency encoded magnetic tape systems.

The variable frequency clock VFC produces a ramp output intended to occur so that each raw data pulse falls at the midpoint of the rise of a ramp. Raw data pulses introduced at terminal 10 are sampled by phase comparator 11 to produce a positive or negative pulse into memory unit 12. This pulse is of an amplitude proportional to the difference between the input magnitude of the ramp voltage and the magnitude of the ramp at the time the raw data pulse is sampled. An analog signal is produced by 12 to bias sawtooth generator 15 and cause slight corrections of the ramp slope so as to move the midpoint of the rise time toward the raw data pulse.

Since the sync pulses occur at regular intervals as shown, the frequency of 15 can be directly proportional to the sync frequency for accurate initial synchronization. However, data pulses can occur with spacing of 1.5 times the sync pulse spacings. Therefore, the frequency of 12 is doubled before data sampling. Control logic 16 samples the initial sync pulse at t0 and holds switch 18 in the position shown until a single-shot circuit has times out. The next pulse thereafter, which occurs at t1, sets a latch in 16 so that 18 is switched, placing resistor 20 in circuit with transistor 17. By setting 20 at half the value of resistor 19, the frequency of 15 is doubled after 18 is switched.

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