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Browse Prior Art Database

Circuit Package

IP.com Disclosure Number: IPCOM000091827D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 95K

Publishing Venue

IBM

Related People

Benenati, J: AUTHOR [+4]

Abstract

The package comprises multipad semiconductor device 1 joined by solder reflow techniques to thin chip carrier 2. This composite structure is joined, also by solder reflow techniques, to a simple or multilayer module 3. Carrier 2 can also be of multilevel construction, with appropriate heat sinks attached. Both the carrier and module can be constructed of ceramic, glass organic, metal materials or composites of these, depending on the particular construction needs. Metallizings 4 are applied by methods such as by screening conductors and firing them, etching metal foil, or electroforming. The thin carrier is prepared to receive the semiconductor chip by providing isolated soldered or solderable areas in the portions of the metallizing to which the chip pads make contact.

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Circuit Package

The package comprises multipad semiconductor device 1 joined by solder reflow techniques to thin chip carrier 2. This composite structure is joined, also by solder reflow techniques, to a simple or multilayer module 3. Carrier 2 can also be of multilevel construction, with appropriate heat sinks attached. Both the carrier and module can be constructed of ceramic, glass organic, metal materials or composites of these, depending on the particular construction needs. Metallizings 4 are applied by methods such as by screening conductors and firing them, etching metal foil, or electroforming. The thin carrier is prepared to receive the semiconductor chip by providing isolated soldered or solderable areas in the portions of the metallizing to which the chip pads make contact.

In one arrangement, the solder on the carrier is a low melting temperature of lead and tin such as the eutectic. The device pads are of a higher melting solder such as pure lead or lead-tin alloys with a high concentration of lead. Alternatively, the solder on the carrier lands comprises 10 tin: 90 lead. Once the chip is joined to the chip carrier, electrical testing can be performed to ensure adequacy of electrical characteristics without any damage to the chip pads. The module contains recesses at the sites where the chip carrier is to be joined. Thus, joints can be made simultaneously to the solderable back of the device as well as to the lands on the chip carrier if desired. Metallizing can be applied to the bottom of the cavity for joining the bank of the device by screening, spraying, preforms, transfer tapes, etc. The bottom of the cavity can also be a metallic heat sink 5. The metallizing on the module can be either tinned or untinned.

In one form, eutectic solder is used on the chip carrier and on the module. The joining of the chip carrier to the module is performed at a temperature suffic...