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Data Storage with SCR Memory Cells

IP.com Disclosure Number: IPCOM000091837D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Schunemann, CH: AUTHOR [+3]

Abstract

Memory cell 1 in this word-organized storage array consists of two one-emitter SCR's with a load resistor 10. The sense amplifiers and bit drivers are located at the PNP side. The word control circuits are placed at the NPN side.

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Data Storage with SCR Memory Cells

Memory cell 1 in this word-organized storage array consists of two one- emitter SCR's with a load resistor 10. The sense amplifiers and bit drivers are located at the PNP side. The word control circuits are placed at the NPN side.

This structure saves power dissipation. The operation mode is a combined trickle current pulse power mode. The stand-by status is trickle current. Since an addressed word is full-powered and the non-addressed words are switched off power, one emitter per device is possible. The input resistance of the sense amplifier is increased by resistor Rb. Thus, a current limiting resistance in the read and write status is realized.

In the trickle current status, a current limitation is performed by the word line resistor Rw and resistors 10 from a cell. The arrangement has the following advantages. There are no multiemitter parasitic problems. There is less peripheral power dissipation. Less space is occupied because of one emitter. There are less tolerance problems because of resistor 10.

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