Browse Prior Art Database

Write Sense Amplifier

IP.com Disclosure Number: IPCOM000091842D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Wiedmann, S: AUTHOR

Abstract

T1 and T2 form a memory cell. Upon the application of an addressing pulse, in this case at A', through the increase of the cell current and consequently also the increase of the voltage drop across RA, the cell information can be read out via the bit line B0 or B1. The sense amplifier is formed by transistors TS1 and TS2 which operate as a differential amplifier, common RE. The readout signal is available at terminals 01 and 02.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 86% of the total text.

Page 1 of 2

Write Sense Amplifier

T1 and T2 form a memory cell. Upon the application of an addressing pulse, in this case at A', through the increase of the cell current and consequently also the increase of the voltage drop across RA, the cell information can be read out via the bit line B0 or B1. The sense amplifier is formed by transistors TS1 and TS2 which operate as a differential amplifier, common RE. The readout signal is available at terminals 01 and 02.

During writing, the bit line potential is decreased by transistors TW1 and TW2 to such an extent that the corresponding T1 or T2, respectively, is switched in. The addressing can also take place at point A with RA abolished. Writing can be performed by one respective transistor switch connected between the emitters of TS1 or TS2 and RE. The feature of this sense amplifier in having TS1 and TS2 consists in that bit line B0 or B1 is coupled directly with the base of the respective sense transistor. Also, by omitting the base voltage divider, the operating point of TS1 or TS2 is floating.

Due to the fact that there is no fixed base bias for TS1 and TS2, the latter can follow any DC voltage shift caused by wide tolerances, e.g., of the collector resistors, etc. The decisive factor is the potential difference exclusively between the base of the memory cell transistor and the emitter of the sense transistor which corresponds to two diodes in series. Through the common emitter resistor RE, a control signal, phase-shifted by...