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Shift Register

IP.com Disclosure Number: IPCOM000091844D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Leal, PR: AUTHOR [+2]

Abstract

In the upper drawing, a nonshifting storage device is used for shifting binary numbers. Nonshifting storage register 10 stores a plurality of binary digits in binary stages 11..14. The outputs of each binary stage are connected to both the A and B inputs of respective stages 16...19 of binary adder 15. The outputs of the respective stages of the adder are connected by lines 36...39 to the inputs of stages 11...14, respectively, of register 10. The binary number stored in register 10 is thus transmitted in parallel to adder 15.

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Shift Register

In the upper drawing, a nonshifting storage device is used for shifting binary numbers. Nonshifting storage register 10 stores a plurality of binary digits in binary stages 11..14. The outputs of each binary stage are connected to both the A and B inputs of respective stages 16...19 of binary adder 15. The outputs of the respective stages of the adder are connected by lines 36...39 to the inputs of stages 11...14, respectively, of register 10. The binary number stored in register 10 is thus transmitted in parallel to adder 15.

The digit from each stage is transmitted to the A and B inputs of the corresponding adder stage so that adder 15 in effect adds the binary number to itself. The resultant sum is then transmitted over lines 36...39 to register 10 and stored. In this manner, the binary number is shifted one stage to the left in register 10.

A different arrangement is shown in the lower drawing. Such employs arithmetic logic unit 64 and storage registers 61...63 to shift binary data to the left for the purpose of obtaining error detection and correction by the logic shown.

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