Browse Prior Art Database

Controller for Data Processing Systems

IP.com Disclosure Number: IPCOM000091845D
Original Publication Date: 1968-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Anderson, DW: AUTHOR [+3]

Abstract

This controller is for data processing systems including a plurality of independent units which can perform different instructions simultaneously. Two or more of these units can use common general purpose storage registers for holding operands or components of addresses. In such systems, the order in which the instructions are executed is variable. This is because instructions previously sent to a unit can be delayed before being executed while executing subsequent instructions in another unit. Therefore, interdependent instructions give rise to problems.

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Controller for Data Processing Systems

This controller is for data processing systems including a plurality of independent units which can perform different instructions simultaneously. Two or more of these units can use common general purpose storage registers for holding operands or components of addresses. In such systems, the order in which the instructions are executed is variable. This is because instructions previously sent to a unit can be delayed before being executed while executing subsequent instructions in another unit. Therefore, interdependent instructions give rise to problems.

Counters UA and UM are provided for each general purpose register, not shown, to interlock the utilization of the associated general purpose register by a dependent instruction prior to the register being used for the preceding instruction. UA prevents the use of the associated general purpose register for address generation. UM prevents a modification of the contents of the associated general purpose registers.

The bits of an instruction relating to an operation code are fed through a set of gates along line 5 to instruction decoder 16 which determines the type of instruction to be performed, the particular type of instruction decoded being indicated by lines 1...5 connected to interlock control 6. The outputs on lines
10...12, controlling the selection of gates for addressing the selected general purpose register, are fed by interlock control 6. The latter also emits signals on lines 13 and 14 for incrementing the associated UA and UM counters.

Information in the R1 field of an instruction is fed from operation register 17 through a set of gates and along a line 20 to a Select UA circuit and to a UM interlock circuit. The latter and UA interlocks 22 and 23 serve to indicate the state of associated UM and UA counters. Data in the R2 and X fields of an instruction is supplied from register 17 through a set of gates along a line 30 to UA interlock 22. Data in the B field of an instruction is fed from register 17 through a set of gates along a line 31 to UA interlock 23. Data in the D field of an instruction is supplied along a line 32 to one input of an adder not shown. The Select UA responds to the four bits of the R1 field selecting only one of 16 output lines connected to the associated And's 43...45. The outputs of these An d's are connected by associated lines 46...48 to the respective UA counters 1...16. Subsequent instructions can be executed out of order if the specified general purpose registers are not reserved by an earlier instruction. In these cases it is necessary for the state of specified UA counters to be sampled to determine whether or not the associated counters contain all zeros, which indicates that the associated general purpose register is available. To this end, lines 60...62 are employed with the associated UA counters 1...16 to indicate to the UA interlock 23 whether their contents are zero or not.

The Select UM resp...