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Partially Encoded Address Mapping Device

IP.com Disclosure Number: IPCOM000091876D
Original Publication Date: 1968-Jun-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

A standard 2,048 word memory matrix 10 is rewired for address mapping by an associative memory as in drawing B. In drawing A, locations in memory 10 are selected by an 11-bit address broken down into a 6-bit page 12 and a 5-bit word 14. The page is decoded by decoders 16 and 18 to provide the X and Y select lines of two-dimensional 8-by-8 decode matrix 20. The output from matrix 20 provides one of 64 lines which apply the X half-select to memory 10. The word 14 of the memory address is decoded by decoders 22 and 24 into the X and Y select of two-dimensional 4-by-8 decode matrix 26. The output of matrix 26 provides one of 32 Y half-select lines to memory 10. In this manner, one of 2,048 words in memory 10 is selected.

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Partially Encoded Address Mapping Device

A standard 2,048 word memory matrix 10 is rewired for address mapping by an associative memory as in drawing B. In drawing A, locations in memory 10 are selected by an 11-bit address broken down into a 6-bit page 12 and a 5-bit word 14. The page is decoded by decoders 16 and 18 to provide the X and Y select lines of two-dimensional 8-by-8 decode matrix 20. The output from matrix 20 provides one of 64 lines which apply the X half-select to memory 10. The word 14 of the memory address is decoded by decoders 22 and 24 into the X and Y select of two-dimensional 4-by-8 decode matrix 26. The output of matrix 26 provides one of 32 Y half-select lines to memory 10. In this manner, one of 2,048 words in memory 10 is selected.

A page address 12 of six or more bits can be mapped into one of the 64 pages in memory 10 by 64-word associative memory 30. This can be accomplished by directly wiring the 64 match outputs from the associative memory on a one-for-one basis to the 64 pages of memory 10. Thus, whenever a word in the associative memory matches the page 12 it can cause a match output on one of the 64 lines thus selecting that page within memory 10. This arrangement is impractical for reasons given below.

In standard memory manufacture, decoders 16, 18, 22, and 24 and decode matrices 20 and 26 can be permanently wired into memory 10 so that modification is impossible. For this reason, it is not possible to bypass decoders 16 and 18...