Browse Prior Art Database

Memory Allocation and Addressing

IP.com Disclosure Number: IPCOM000091889D
Original Publication Date: 1968-Jun-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 4 page(s) / 61K

Publishing Venue

IBM

Related People

Palounek, LR: AUTHOR

Abstract

The drawing shows an addressing system for contiguously addressing, i.e., sequentially addressing through all storage modules, the main storage of data processing systems. The addressing system functions under differing overall main storage address field sizes, functions with different memory modules exhibiting different speeds or different field sizes, and functions with different memory module configuration. The sum of the module field sizes totals the overall field size.

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Memory Allocation and Addressing

The drawing shows an addressing system for contiguously addressing, i.e., sequentially addressing through all storage modules, the main storage of data processing systems. The addressing system functions under differing overall main storage address field sizes, functions with different memory modules exhibiting different speeds or different field sizes, and functions with different memory module configuration. The sum of the module field sizes totals the overall field size.

The main storage consists partially of memory modules M0...M7. Each module consists of a magnetic core memory having a nominal 128K field of addresses. Thus, the eight totalled together present an overall address field of nominally 1,024K, or actually 1,048,576, addressable memory locations. In addition to the eight modules, the overall address field includes an additional high-speed memory module HS1 nominally of 32K size or alternatively a high- speed module HS2 of some other size, e.g., nominally 64K.

In one form of operation, HS1 is associated with one central processing unit, not shown, and HS2 is associated with a second central processing unit, not shown, with some or all of the modules M0...M7 shared by both processing units. Where HS1 and HS2 are different sizes, the system employing the smaller module usually has a gap of invalid addresses in order to preserve the same physical location for corresponding addresses in each processing unit. For example, HS1 can operate with addresses between 32K-and 64K being invalid. Here, however, HS2 is initially ignored and the addresses 32K to 64K are considered valid.

Although main storage is organized as a composite of memory modules having different speeds and different sizes and which can exist in different configurations, those differences are transparent to the data processing system. This is because the addressing system of the drawing organizes the memory modules so as to form an overall contiguous address field as a composite of each memory module field. For example, by using the M0...M7 and HS1 modules as the total main storage for a first processing unit, an overall field of 1,056K is established. This overall field is addressed by the twenty address bits Bit 1...Bit
20.

The low-order addresses up to 32K are located in HS1. The next 128K addresses are in a module such as M1. The next 128K addresses are in M2, etc. HS1 is selected for the first processing unit by control unit 1 via line 2 to gate 4 with gate 5 and HS2 not being selected. When the address specified by the address bits is between 0 and 32K, M0...M7 is selected and gate 4 is automatically opened. When the address selected by the address bits exceeds the 32K capacity of HS1, the appropriate one of M1...M7 is selected.

The particular module selected is determined by the high-order address bits Bit 1...Bit 3. For example, an address in the 165K range has high-order binary address bits 001 which are supplied to s...