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Bipolar Variable Holdover Delay

IP.com Disclosure Number: IPCOM000091910D
Original Publication Date: 1968-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Burggraff, MA: AUTHOR

Abstract

In this double-ended delay circuit, the output does not go up until the input is up for a predetermined length of time. This is termed the positive delay. Once the output goes up, the circuit reverses itself and does not go down until the input goes down and stays down for a predetermined length of time. This is termed the negative delay. All positive or negative pulses of too short a duration are ignored. Both the positive and negative delays are independently adjustable. The time constant established by C1, with R1 and R2 determines the positive-going delay. The time constant established by C2, with R3 and R4, determines the negative-going delay. INV1 and INV2 are inverters. AI2 and AI4 are And-Inverters. AI2 and AI4 consist of a single transistor which acts as an And followed by an Inverter.

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Bipolar Variable Holdover Delay

In this double-ended delay circuit, the output does not go up until the input is up for a predetermined length of time. This is termed the positive delay. Once the output goes up, the circuit reverses itself and does not go down until the input goes down and stays down for a predetermined length of time. This is termed the negative delay. All positive or negative pulses of too short a duration are ignored. Both the positive and negative delays are independently adjustable. The time constant established by C1, with R1 and R2 determines the positive- going delay. The time constant established by C2, with R3 and R4, determines the negative-going delay. INV1 and INV2 are inverters. AI2 and AI4 are And- Inverters. AI2 and AI4 consist of a single transistor which acts as an And followed by an Inverter.

If the input is negative, D1 clamps T1 off. The output of T1 inverts through AI4 and the output is negative. When the input goes positive, D1 allows T1 to turn on. However, the negative pulse from C1 holds T1 off until it times out. AI2 is gated off at this time.

Therefore, C2 has no affect on the circuit. After C1 times out, it allows T1 to turn on causing the output to go positive. This completes the positive delay cycle. Once the output is positive, AI2 is gated on and AI4 gates out the effects of C1 on the circuit.

If the input goes negative. D2 allows T2 to turn on. However, the negative pulse from C2 holds T2 off until it times out....