Browse Prior Art Database

Data Configuration and False Start Rejection for Magnetic Recording

IP.com Disclosure Number: IPCOM000091939D
Original Publication Date: 1968-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Andrews, DR: AUTHOR [+3]

Abstract

This is a data character representation for magnetically recorded phase-encoded data characters. A detection technique is utilized to eliminate stray noise signals occurring between adjacent data characters and to provide a start signal for the self-clocked data bits.

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Data Configuration and False Start Rejection for Magnetic Recording

This is a data character representation for magnetically recorded phase- encoded data characters. A detection technique is utilized to eliminate stray noise signals occurring between adjacent data characters and to provide a start signal for the self-clocked data bits.

The recorded flux pattern of a typical data character is depicted in waveform A and comprises a plurality of flux changes occurring at a periodic interval T. The direction of change is representative of binary information recorded. The binary bits representative of a data character are preceded by a prelude pattern comprising a positive-going transition followed T/2 later by a negative-going transition.

The recorded flux signal is sensed by a magnetic transducer. This provides a signal representative of the rate of change of flux with respect to time as depicted in waveform B. The signal of waveform B is amplified, differentiated, and inverted to appear as waveform C. This is applied as an input to coincidence circuits 1 and 2 which are gated by the out-of-phase and in-phase outputs of flip- flip 3 respectively. Flip-flop 3 is set on at the end of a preceding data character, thus gating coincidence circuit 2 and degating coincidence circuit 1. When waveform C goes negative as indicated at 30, lower detector 4 provides a signal which resets flip-flop 3 to gate circuit 1 and degate circuit 2. The out-of-phase signal of flip-flop 3 is applied to T/4 time delay 5.

When signal C reaches a positive amplitude as indicated at point 31, upper detector 6 provides an output which is gated by Or 7 to set flip-flop 3 thus degating circuit 1 and gating circuit 2. The positive output is applied to coincidence circuit 8 with the output of T/4 delay 5 to provide an output signal which is applied to T/2 delay 9. Then waveform C goes negative and, upon reaching point 32, detector 4 resets flip-flop 3. This...