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Browse Prior Art Database

High Speed Binary Adder

IP.com Disclosure Number: IPCOM000091950D
Original Publication Date: 1968-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 95K

Publishing Venue

IBM

Related People

Weinberger, A: AUTHOR

Abstract

This 64-place binary adder, with end-around carry, achieves high operating speed through efficient organization of the carry look-ahead logic functions. The basic logic element is the Nor-Or current switch, at A. This circuit has a finite predetermined delay characteristic between its inputs and outputs. Dotting functions which involve relatively small delay are shown at B and C. The in-phase Or outputs of current switches have a fan-out capacity of connection to inputs of ten other current switches, either directly, or through Dot-And junctures, or through cascade connected pairs of Dot-And and Dot-Or junctures. The out-phase Nor outputs of these switches are also extensible to inputs of ten other switches, but only directly or through Dot-Or junctures.

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High Speed Binary Adder

This 64-place binary adder, with end-around carry, achieves high operating speed through efficient organization of the carry look-ahead logic functions. The basic logic element is the Nor-Or current switch, at A. This circuit has a finite predetermined delay characteristic between its inputs and outputs. Dotting functions which involve relatively small delay are shown at B and C. The in- phase Or outputs of current switches have a fan-out capacity of connection to inputs of ten other current switches, either directly, or through Dot-And junctures, or through cascade connected pairs of Dot-And and Dot-Or junctures. The out- phase Nor outputs of these switches are also extensible to inputs of ten other switches, but only directly or through Dot-Or junctures. The Dot-Or output has a fan-out extension capability of ten current switch inputs, but with no intervening switches or junctures. Dot-And outputs are extensible to ten current switches either directly or through Dot-Or junctures.

The adder requires only four levels of cascaded current switches in the path from any pair of addend-augend input bits to the outlet for the corresponding sum bit representation. In the first level in D, the addend and augend bits Aj, Bj, where j=0, 1...63 with 0 denoting the most significant bit, are logically manipulated in quaternary 4-bit groups such as A4i, B4i, A4i+1, B4i+1, A4i+2, B4i+2, A4i+3, B4i+3 where i=0, 1...15. The first level logic produces repre...