Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Computer Error Anticipator

IP.com Disclosure Number: IPCOM000091987D
Original Publication Date: 1968-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Carnevale, RJ: AUTHOR [+7]

Abstract

The continuous operation of a central processing unit CPU is interrupted for a brief period in response to an indication that the noise level in a microprogram control store is likely to cause an error in the ensuing CPU cycle. Control store array 10 passes program signals cyclically through sense amplifier 12 and latches 14 to register 16. The contents of the latter, along with clock pulses from main clock 20, control the gating activity of the CPU for the ensuing CPU cycle. An indication of the level of noise in array 10 occurs in the form of a ground shift on ground line connection 26 and is detected by threshold detector 22 which triggers a noise latch 28. When latch 28 is triggered, the clock 20 is disabled, preventing the registers of CPU from changing their contents and thus creating a pause in the CPU operation.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Computer Error Anticipator

The continuous operation of a central processing unit CPU is interrupted for a brief period in response to an indication that the noise level in a microprogram control store is likely to cause an error in the ensuing CPU cycle. Control store array 10 passes program signals cyclically through sense amplifier 12 and latches 14 to register 16. The contents of the latter, along with clock pulses from main clock 20, control the gating activity of the CPU for the ensuing CPU cycle. An indication of the level of noise in array 10 occurs in the form of a ground shift on ground line connection 26 and is detected by threshold detector 22 which triggers a noise latch 28.

When latch 28 is triggered, the clock 20 is disabled, preventing the registers of CPU from changing their contents and thus creating a pause in the CPU operation. Auxiliary clock source 30 is enabled to provide clocking for the units, such as the control store, which are to continue cycling during the pause. When the noise abates, clock 20 is enabled and CPU operation continues with the program step which was being initiated when the CPU operation was interrupted, i.e., there is a retry of the last step.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]