Browse Prior Art Database

Computer Error Anticipator and Cycle Extender

IP.com Disclosure Number: IPCOM000091988D
Original Publication Date: 1968-Jul-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Hartlipp, WE: AUTHOR [+4]

Abstract

A computer is stopped in response to a signal indicating the probable next cycle error until there is no longer any likelihood of an error. In response to the sensing of an excessive level of noise in microprogram control store 12 occurring at a time during which it can affect the microprogram control signals which control the ensuing computer cycle, the computer operation is interrupted. When excessive noise is detected in control 12, latch 40 and auxiliary noise latch 42 are triggered. The latch 42 outputs prevent the clock pulses from entering new data into registers 14 and latches 18 and also prevent a change of contents of registers 24 and 26 which hold the microprogram control signals.

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Computer Error Anticipator and Cycle Extender

A computer is stopped in response to a signal indicating the probable next cycle error until there is no longer any likelihood of an error. In response to the sensing of an excessive level of noise in microprogram control store 12 occurring at a time during which it can affect the microprogram control signals which control the ensuing computer cycle, the computer operation is interrupted. When excessive noise is detected in control 12, latch 40 and auxiliary noise latch 42 are triggered. The latch 42 outputs prevent the clock pulses from entering new data into registers 14 and latches 18 and also prevent a change of contents of registers 24 and 26 which hold the microprogram control signals. The write cycle of main store 20 is delayed from the end of the read cycle by an amount equal to the number of cycles the computer logic is interrupted. Thus the computer logic and store 20 are maintained in proper timing relationship. All words read out of local store 22 during the interruption are regenerated back into such store for use after the interruption. Latches 40 and 42, whose outputs control the interruption process, are rendered ineffective during a channel break-in process. At such time, the control signal is the result of a hardware line rather than the control store output.

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