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Depositing Pd Ohmic Contact Layers on Semiconductor Devices

IP.com Disclosure Number: IPCOM000091992D
Original Publication Date: 1968-Aug-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Totta, PA: AUTHOR

Abstract

This method facilitates the depositing of a Pd ohmic contact layer in contact holes in an encapsulating oxide layer for a device. In various contact metallurgy systems for semiconductor devices, an ohmic contact layer between the conductor metallurgy stripe and the semiconductor surface is required. Such ohmic contact layers are typically formed by depositing Pt on the wafer, sintering to form Pt(x) Si(x) in the holes, and subsequently etching in aqua regia to take away the excess unreacted Pt of the oxide. However, the sintering of Pt, normally done at 550 degrees to 700 degrees C, can cause undesirable changes in the distribution of the doping impurities in the device.

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Depositing Pd Ohmic Contact Layers on Semiconductor Devices

This method facilitates the depositing of a Pd ohmic contact layer in contact holes in an encapsulating oxide layer for a device. In various contact metallurgy systems for semiconductor devices, an ohmic contact layer between the conductor metallurgy stripe and the semiconductor surface is required. Such ohmic contact layers are typically formed by depositing Pt on the wafer, sintering to form Pt(x) Si(x) in the holes, and subsequently etching in aqua regia to take away the excess unreacted Pt of the oxide. However, the sintering of Pt, normally done at 550 degrees to 700 degrees C, can cause undesirable changes in the distribution of the doping impurities in the device. Further, other difficulties are presented in the evaporating of Pt, particularly in stripping the excess Pt with hot aqua regia followed by a hot chromic acid and buffered etch.

This process of forming an ohmic contact in openings in the encapsulation layer consists of these steps. A thin layer of SiO(2) is sputter-deposited over the phosphosilicate glass encapsulating layer. Contact holes in the layer are opened to expose the semiconductor surface. A layer of Pd is deposited over the SiO(2) layer and into the holes, such layer being approximately 500 angstroms in thickness. The Pd is sintered in the holes by heating to approximately 350 degrees to 550 degrees C to form palladium silicide. The wafer is dipped in a buffer etch. The etch r...