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Checking Digital System Clock Pulses

IP.com Disclosure Number: IPCOM000092021D
Original Publication Date: 1968-Aug-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Brown, PJ: AUTHOR [+2]

Abstract

The clock pulse checker verifies cyclically that all pulse phases of a cyclic clock element of a digital system clock are generated in correct form and phase sequence and that no extraneous pulses occur during the sequence. In transitions between phases, it is recognized that there is overlapping in pulse phases and this is taken into consideration in the checking logic.

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Checking Digital System Clock Pulses

The clock pulse checker verifies cyclically that all pulse phases of a cyclic clock element of a digital system clock are generated in correct form and phase sequence and that no extraneous pulses occur during the sequence. In transitions between phases, it is recognized that there is overlapping in pulse phases and this is taken into consideration in the checking logic.

Shown at A is the logic for checking a clock system with phases CLK A, CLK B, CLK C, CLK D. Error indication is produced if the clock phase inputs do not assume the sequence of combinational states shown in this table. State No.

CLK A CLK B CLK C CLK D 1 0 0 0 0 2 1 0 0 0 *2a 0 0 0 0 *2b 1 1 0 0 3 0 1 0 0 *3a 0 1 1 0 *3b 0 0 0 0 4 0 0 1 0 4a 0 0 1 1 4b 0 0 0 0 5 0 0 0 1 *5a=1 0 0 0 0 *5b 1 0 0
1. *permissible but not mandatory transitional states.

The logic at A is responsive only to the system clock pulses and system and error reset pulses. No other impulses, e.g., gating impulses, are needed to control the logic. When all clocks are off, as in state 1, the logic detects as an error condition the occurrence of a combinational clock state other than states 2, 2a or 2b.

Similarly, after each other state 2...5 the system detects error as the occurrence of other than the next listed state or allowable transitional phases. The last error indicating stage includes feedback connections to establish a latching, trigger, operation. Thus a reset condition is held until...