Browse Prior Art Database

Control of Threshold in N Channel FET Integrated Circuit

IP.com Disclosure Number: IPCOM000092026D
Original Publication Date: 1968-Aug-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Fowler, AB: AUTHOR [+3]

Abstract

This method controls the surface potential along a Si-SiO(2) interface to attain a low threshold voltage, e.g., -5V to +5V, for N-channel MOS field effect transistors and, simultaneously, a high-threshold voltage, e.g., 30V to 40V, for the interconnection region of an integrated arrangement.

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Control of Threshold in N Channel FET Integrated Circuit

This method controls the surface potential along a Si-SiO(2) interface to attain a low threshold voltage, e.g., -5V to +5V, for N-channel MOS field effect transistors and, simultaneously, a high-threshold voltage, e.g., 30V to 40V, for the interconnection region of an integrated arrangement.

MOS field effect transistor 1 comprises P-type Si wafer 3 having source and drain electrodes 5 and 7 diffused in one surface. Gate electrode 9 is insulated from the surface of wafer 3 intermediate electrodes 5 and 7, i.e., the conduction channel 11, by gate insulator 13, e.g., SiO(2). Insulator 13 is generally thinner than the SiO(2) insulating layer 15 formed over remaining surface portions of wafer 3 defining the interconnection region. Layer 15 is employed as a mask during diffusion of electrodes 5 and 7 and, also, to isolate metallic patterns 17 interconnecting source 5, drain 7, and electrode 9 with other transistors, not shown, formed in wafer 3.

Generally, the surface of wafer 3 adjacent Si-SiO(2) interface 19 is inverted and transistor 1 exhibits depletion-mode operation.

Subsequent to forming insulator 13 and prior to the metallization of electrode 9, gold is diffused from the rear surface of wafer 3, as indicated by the arrows, which tends to accumulate along interface 19, i.e., the transition region between wafer 3 and insulator 13 and, also, layer 15. Since gold diffuses into wafer 3 in a negatively-charged...