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Triple Ramp Analog To Digital Converter with Reverse Direction Third Ramp

IP.com Disclosure Number: IPCOM000092110D
Original Publication Date: 1968-Sep-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Walton, CA: AUTHOR

Abstract

In this integrating ramp analog-to-digital converter, an unknown analog signal is coupled to input terminal 10 through switch 12 to the input of amplifier 14. In conjunction with capacitor 16 and resistor 18, amplifier 14 comprises an integrator. The unknown analog signal is integrated for a time equal to that required for pulses from oscillator 20 to be coupled through And 21 to step counter 22 to a predetermined count such as full scale to produce the waveform from T1 to T2. The control signals to operate the switches and gates are provided by control circuits 30. The first reference voltage Vr of the opposite polarity to the unknown voltage is then applied to the input of amplifier 14 by turning on switches 24 and 26 and counter 22 is reset.

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Triple Ramp Analog To Digital Converter with Reverse Direction Third Ramp

In this integrating ramp analog-to-digital converter, an unknown analog signal is coupled to input terminal 10 through switch 12 to the input of amplifier
14. In conjunction with capacitor 16 and resistor 18, amplifier 14 comprises an integrator. The unknown analog signal is integrated for a time equal to that required for pulses from oscillator 20 to be coupled through And 21 to step counter 22 to a predetermined count such as full scale to produce the waveform from T1 to T2. The control signals to operate the switches and gates are provided by control circuits 30. The first reference voltage Vr of the opposite polarity to the unknown voltage is then applied to the input of amplifier 14 by turning on switches 24 and 26 and counter 22 is reset. The reference signal is integrated while pulses from oscillator 20 are gated through And 21 to counter 22 from T2 to T3. The output of amplifier 14 is coupled to comparator circuit 28 which is referenced to the initial voltage such as ground potential. An equal- compare condition generates a signal which is coupled to circuits 30. The occurrence of the next output pulse from oscillator 20 at T4 conditions circuits 30 to produce an output. This disconnects reference voltage Vr at time T4 and closes switch 36 to couple a second reference voltage -Vr/k of the same polarity as the unknown analog signal to the input of amplifier 14, and to condition And 3...