Browse Prior Art Database

Serial Parallel Parity for Error Correction in Read Write Store

IP.com Disclosure Number: IPCOM000092115D
Original Publication Date: 1968-Sep-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Conzola, JS: AUTHOR [+2]

Abstract

This system uses a two-dimensional parity method for error correction in either a one- or two-dimensional system. Store 1 is divided into blocks as shown. The larger the blocks, the more efficient the system becomes from the bit usage point of view. However, larger blocks become more difficult to handle because of the extra time or hardware involved. Each block represents a sequence of bytes or words. It is not essential that there be consecutive addresses but this is the usual case. For the greatest convenience, the blocks contain addresses which are commonly read simultaneously or in sequence.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 84% of the total text.

Page 1 of 2

Serial Parallel Parity for Error Correction in Read Write Store

This system uses a two-dimensional parity method for error correction in either a one- or two-dimensional system. Store 1 is divided into blocks as shown. The larger the blocks, the more efficient the system becomes from the bit usage point of view. However, larger blocks become more difficult to handle because of the extra time or hardware involved. Each block represents a sequence of bytes or words. It is not essential that there be consecutive addresses but this is the usual case. For the greatest convenience, the blocks contain addresses which are commonly read simultaneously or in sequence.

Each block is arranged with a parity bit m for each word and a parity bit n for each bit position in the word. Assume a block size of seventy-two bits arranged in eight bytes of nine bits each. The data is read from cores either simultaneously or in parallel and loaded into register 2. The data is then applied to Exclusive-Or's 3...20. Each such circuit combines the input signals as shown with reference to Exclusive-Or 20. Circuits 3...10 operate to combine the bits in the same byte, i.e., horizontal. Circuits 11...20 combine the corresponding bits in all the bytes, i.e., vertical. The output signals from these horizontal and vertical circuits are then combined in And's 21...92. The output of each And feeds a bit position in register 93.

To correct for errors, the output of register 93 is combined with the da...