Browse Prior Art Database

Fabricating Field Effect Transistors

IP.com Disclosure Number: IPCOM000092119D
Original Publication Date: 1968-Sep-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Statz, H: AUTHOR

Abstract

This method is for fabricating a field effect transistor in which the conduction channel is formed by an out-diffusion process. To fabricate a unipolar field effect transistor, frame-like P-type zone 1 is diffused into the surface of high-resistivity, Cr-doped GaAs substrate 3, e.g., in the order of 10/8/ ohms per centimeter or having a Cr concentration of less than 3 x 10/17/ cm/-3/. Thin layer 5 of silicon dioxide, e.g., between 1000 angstroms and 2000 angstroms is formed over the surface of substrate 3. The latter is then heated from one to two hours at a temperature between 900 degrees C and 1050 degrees C in an evacuated atmosphere. During such heat treatment, a thin N-type layer 7 of approximately 1 micron is produced along the surface of substrate 3.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 68% of the total text.

Page 1 of 2

Fabricating Field Effect Transistors

This method is for fabricating a field effect transistor in which the conduction channel is formed by an out-diffusion process. To fabricate a unipolar field effect transistor, frame-like P-type zone 1 is diffused into the surface of high-resistivity, Cr-doped GaAs substrate 3, e.g., in the order of 10/8/ ohms per centimeter or having a Cr concentration of less than 3 x 10/17/ cm/-3/. Thin layer 5 of silicon dioxide, e.g., between 1000 angstroms and 2000 angstroms is formed over the surface of substrate 3. The latter is then heated from one to two hours at a temperature between 900 degrees C and 1050 degrees C in an evacuated atmosphere. During such heat treatment, a thin N-type layer 7 of approximately 1 micron is produced along the surface of substrate 3. Layer 7 constitutes the conduction channel of the field effect transistor. Due to the heat treatment, Cr atoms close to the surface diffuse in an outward direction and are gettered by layer 5. Zone 1 has a sufficiently high-impurity concentration so as not to be inverted during the heat treatment. The depth and conductivity of layer 7 depend upon the Cr concentration at the surface of substrate 3, the thickness of layer 5, and on duration and temperature of heat treatment. Ohmic source and drain contacts 9 and 11 are deposited by evaporation techniques through windows 13 and 15 etched in layer 5. Also, window 17 is etched in layer 5 intermediate source and drain contacts 9...