Browse Prior Art Database

Regulator for Memory

IP.com Disclosure Number: IPCOM000092134D
Original Publication Date: 1968-Sep-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Davis, DE: AUTHOR [+2]

Abstract

Drawing A shows a shunt voltage regulator that maintains a preset voltage between terminal 2 and ground. A load, not shown, is connected between point 2 and a regulated higher potential point 3. Transistors 4 and 5 are connected with a resistor 6 to conduct between point 2 and ground and are controlled to maintain the preselected voltage. Resistor 7 is also connected between point 2 and ground. Thus current flows from point 3, through the load to point 2, and through transistor 5 and resistor 7 to ground.

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Regulator for Memory

Drawing A shows a shunt voltage regulator that maintains a preset voltage between terminal 2 and ground. A load, not shown, is connected between point 2 and a regulated higher potential point 3. Transistors 4 and 5 are connected with a resistor 6 to conduct between point 2 and ground and are controlled to maintain the preselected voltage. Resistor 7 is also connected between point 2 and ground. Thus current flows from point 3, through the load to point 2, and through transistor 5 and resistor 7 to ground.

Transistors 9 and 10 are connected with resistor 12 as a differential amplifier to control conduction of transistors 4 and 5. Resistors 13 and 14 are connected between point 3 and ground to provide a reference voltage that is applied to the base terminal of transistor 9. The reference voltage varies with any variation of the voltage of point 3 and thus tends to maintain the voltage between points 2 and 3 uniform. The base terminal of transistor 10 is connected to point 2 by wires, not shown, that are external to the regulator. Thus the current at the collector terminal of transistor 9 varies with the voltage at point 2. The collector terminal of transistor 9 is coupled to the base terminal of transistor 4 by resistor and capacitor network 15 and 16. The latter slows the response of the circuit.

The voltage at the base terminal of transistor 4 is maintained slightly above ground by the substantially constant voltage drop across the base-emitt...