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FET Parallel Decoder

IP.com Disclosure Number: IPCOM000092150D
Original Publication Date: 1968-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Lane, R: AUTHOR [+3]

Abstract

The use of complimentary pulses in parallel decoders limits power dissipation in the decoder to transient power and minimizes the time from a new address until an output is achieved. Initially node A is charged to voltage V2 by biasing FET Q1 conductive with the timing pulse. Though address input FET's Q4...Qn can be on at this time, no conduction of voltage V2 to ground takes place since FET Q2 is off. Once node A is charged, the inverted timing pulse is applied to the gate of Q2 rendering Q2 conductive. If no selection is made, at least one of FET's Q4...Qn is also conductive while Q2 is on thus providing a low impedance path to ground and discharging node A. If a selection is made, all FET's Q4...Qn are off thus leaving node A charged.

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FET Parallel Decoder

The use of complimentary pulses in parallel decoders limits power dissipation in the decoder to transient power and minimizes the time from a new address until an output is achieved. Initially node A is charged to voltage V2 by biasing FET Q1 conductive with the timing pulse. Though address input FET's Q4...Qn can be on at this time, no conduction of voltage V2 to ground takes place since FET Q2 is off. Once node A is charged, the inverted timing pulse is applied to the gate of Q2 rendering Q2 conductive. If no selection is made, at least one of FET's Q4...Qn is also conductive while Q2 is on thus providing a low impedance path to ground and discharging node A. If a selection is made, all FET's Q4...Qn are off thus leaving node A charged. To determine whether node A is charged or not, the high-order select can be applied to the drain of FET Q3. If a selection is made, Q3 is biased conductive by voltage V2 to provide a signal to the decoder output. If no selection is made, Q3 does not conduct.

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