Browse Prior Art Database

Address Prefixing

IP.com Disclosure Number: IPCOM000092164D
Original Publication Date: 1968-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Camoin, RJ: AUTHOR [+4]

Abstract

In a multiprocessor system, a channel can perform operations with more than one central processing unit CPU. Therefore, the identity of the CPU that initiates an operation must be preserved. Communication between multiplexor channel 10 and multiprocessor system 12 is performed by means of channel control unit CCU 14. Three incoming multiplex lines, added to the CPU interface 16, are CPU identity ID line 1, CPU ID line 2, and CPU ID line parity. These lines identify which CPU in the system is selecting the channel or which CPU is accepting the channel interrupt response.

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Address Prefixing

In a multiprocessor system, a channel can perform operations with more than one central processing unit CPU. Therefore, the identity of the CPU that initiates an operation must be preserved. Communication between multiplexor channel 10 and multiprocessor system 12 is performed by means of channel control unit CCU 14. Three incoming multiplex lines, added to the CPU interface 16, are CPU identity ID line 1, CPU ID line 2, and CPU ID line parity. These lines identify which CPU in the system is selecting the channel or which CPU is accepting the channel interrupt response.

Three outgoing simplex lines, added to the bus control unit BCU interface 18, are data ID line 1, data ID line 2, and data ID line parity. These ID lines are active when the channel sends a storage request to CCU. The lines thus identify a storage operation as belonging to a specific CPU.

Address prefixing enables the system to identify which CPU is now communicating with or last communicated with any device 20 selected by the multiplexor channel. Each time the channel requests a storage operation, the ID bits are transmitted along with the storage address for that channel. For example, when a start I/O instruction is executed, the ID bits from the CPU are gated to a channel ID register in the multiplexor channel. The program in the initiating CPU has stored at address location 72 a channel address word CAW which must now be fetched by the channel. To do this, the channel places ...