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Data Encoding Circuit

IP.com Disclosure Number: IPCOM000092172D
Original Publication Date: 1968-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Franchini, RC: AUTHOR [+2]

Abstract

The circuitry encodes binary data into modified MFM data. This method of encoding is described in the IBM Technical Disclosure Bulletin, Vol. 10, p. 112. In drawing 1, modified MFM comprises MFM encoding modified by skipping alternate transitions in a string of 0's. The rules are to write data transitions comprising 1's in the center of the bit cell and clock transitions comprising 0's at the leading edge of the bit cells. Those 0's immediately preceded by a 1 or by a 0 having a recorded transition are skipped. The circuit of drawing 2 comprises standard MFM encoding circuitry additionally employing two latches 10 and 11 for blocking alternate clock bits. Latch 10 detects a recorded clock bit and conditions latch 11. The latter blocks the next clock by blocking And 12 and resets latch 10.

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Data Encoding Circuit

The circuitry encodes binary data into modified MFM data. This method of encoding is described in the IBM Technical Disclosure Bulletin, Vol. 10, p. 112. In drawing 1, modified MFM comprises MFM encoding modified by skipping alternate transitions in a string of 0's. The rules are to write data transitions comprising 1's in the center of the bit cell and clock transitions comprising 0's at the leading edge of the bit cells. Those 0's immediately preceded by a 1 or by a 0 having a recorded transition are skipped. The circuit of drawing 2 comprises standard MFM encoding circuitry additionally employing two latches 10 and 11 for blocking alternate clock bits. Latch 10 detects a recorded clock bit and conditions latch 11. The latter blocks the next clock by blocking And 12 and resets latch 10.

Serial input data is supplied on line 13 to shift register 14 and 15. Basic timing is provided by oscillator 16 which undergoes two complete square-wave oscillations per bit cell. Trigger 17 responds by supplying four outputs. A is for the first quarter of the bit cell, B for the second half of the bit cell, C for the first half of the bit cell, and D for the third quarter of the bit cell. Single-shot 18 responds by supplying a short strobe pulse at the beginning and at the middle of the bit cell. A data input, for example, a 1, is supplied on line 13 and output A of trigger 17 inserts the 1 in register 14, causing output A of register 14 to turn on. Output B of trigger 17 and output A of register 14 gate the middle strobe pulse from single-shot 18 through And 19 and Or 20 to change the state of trigger 21 to provide output 22, drawing 1, on line 23.

Output D of trigger 17 conditions shift register 14 and 15 and the follow...