Browse Prior Art Database

Automatic Branch and Link

IP.com Disclosure Number: IPCOM000092226D
Original Publication Date: 1968-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Cordero, H: AUTHOR

Abstract

Data processing systems, which utilize sequential storage addressing, commonly have an adder or incrementing circuit associated with the storage address register. This is a convenient manner of generating the sequential addresses but introduces complications when a branch operation is performed. This system has basic storage unit 1 which is addressed according to the value in main address register 2. Incrementing circuit 3 develops the next sequential address and transfers it back into register 2. A branch operation is detected by decoder 4 connected to control register 5. An output signal on line 6 indicates that a branch operation is to be performed. This signal conditions certain address lines in address circuits 7 for local storage 8.

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Automatic Branch and Link

Data processing systems, which utilize sequential storage addressing, commonly have an adder or incrementing circuit associated with the storage address register. This is a convenient manner of generating the sequential addresses but introduces complications when a branch operation is performed. This system has basic storage unit 1 which is addressed according to the value in main address register 2. Incrementing circuit 3 develops the next sequential address and transfers it back into register 2. A branch operation is detected by decoder 4 connected to control register 5. An output signal on line 6 indicates that a branch operation is to be performed. This signal conditions certain address lines in address circuits 7 for local storage 8. The same signal is also effective to condition And 9 for the transfer of the address value in register 2.

The high-order digits are gated directly into storage through Or 10. The low-order digits from register 2 must be incremented to indicate the next sequential instruction after the branch. This is effected by placing the low-order digits in data register 11 which serves as an input register for arithmetic logic unit ALU 12. The output signal on line 6 conditions ALU 12 to increment the value in register 11 by two. The incremented value, representing the low-order portion of the next sequential address, passes through Or 10 to be stored in storage 8. Since incrementer 3 is not used for this operation,...