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Browse Prior Art Database

Storage Module Reconfiguration to Bypass Bit Failures

IP.com Disclosure Number: IPCOM000092230D
Original Publication Date: 1968-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Bouricius, WG: AUTHOR [+4]

Abstract

This method employs spare storage bit planes, reconfiguration networks, and status registers for use with error-correcting codes to extend their effectiveness or for use with diagnostic tests to extend the useful life of a storage module.

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Storage Module Reconfiguration to Bypass Bit Failures

This method employs spare storage bit planes, reconfiguration networks, and status registers for use with error-correcting codes to extend their effectiveness or for use with diagnostic tests to extend the useful life of a storage module.

Drawing A is a block diagram of this type of storage system. Basic Operating Module BOM can contain any writable storage medium, e.g., cores, plated wires, thin films, flip-flops, etc. At the BOM input there is an Input Reconfiguration Network IRN and its associated Input Status Register IRS. Similarly, the output has an Output Reconfiguration Network ORN and Output Status Register OSR. At all times, other than during an actual change in configuration, ISR and OSR are identical. Attached to the output bus there can be an error corrector, depending on whether or not the data is coded.

It is assumed that the width of the data path is q and that m = 3 spare bit planes are included in BOM. This latter assumption is not a restriction to the method and different arrangements are straight-forward. Then for each of the q data lines there are two bits in each of the status registers, i.e., for line i there are ISR(i1), ISR(i2), and OSR(i1), OSR(i2) as in drawing C. These bits are used to record which bit plane in BOM this particular data line is connected to, either its primary plane or one of its three possible alternates. Drawing B shows typical logic cells used in IRN and ORN to perform the actual switching which maps the q data lines into the q + 3 available storage planes.

During initial operation, when no failures have occurred, all entries in ISR and OSR are zero. As storage planes fail, b...