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Browse Prior Art Database

Chip Selection Mode

IP.com Disclosure Number: IPCOM000092252D
Original Publication Date: 1968-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR [+2]

Abstract

In order to save space on a monolithic memory chip, the chip select signal, rather than being applied to each individual multiemitter transistor, is logically linked with the address signals in a preceding step. The drawing shows a portion of a decoder for a 4 x 4 memory array. Particularly advantageous at a high degree of integration is the saving in space obtained by eliminating one emitter per multiemitter transistor and the associated lines in an area which is densely wired. The only additional circuitry needed is driver D which is disposed in a less densely wired area. The two Dot-Or functions are represented by an electric connection of two lines.

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Chip Selection Mode

In order to save space on a monolithic memory chip, the chip select signal, rather than being applied to each individual multiemitter transistor, is logically linked with the address signals in a preceding step. The drawing shows a portion of a decoder for a 4 x 4 memory array. Particularly advantageous at a high degree of integration is the saving in space obtained by eliminating one emitter per multiemitter transistor and the associated lines in an area which is densely wired. The only additional circuitry needed is driver D which is disposed in a less densely wired area. The two Dot-Or functions are represented by an electric connection of two lines.

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