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Dual Mode Machine Language Programming

IP.com Disclosure Number: IPCOM000092266D
Original Publication Date: 1968-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Deutsch, H: AUTHOR [+4]

Abstract

In data processors having a plurality of instructions, some of which address single-word length operands and others of which address double-word length operands, both addresses being in a base-displacement form, addressing efficiency can be increased by elimination of nonsignificant address digits. Double-word addressing normally requires that the rightmost bit be set to zero. Therefore, a given number of bits in the displacement part of an address can address a block of only one half as many operands in double-word format as can be addressed in a single-word format.

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Dual Mode Machine Language Programming

In data processors having a plurality of instructions, some of which address single-word length operands and others of which address double-word length operands, both addresses being in a base-displacement form, addressing efficiency can be increased by elimination of nonsignificant address digits. Double-word addressing normally requires that the rightmost bit be set to zero. Therefore, a given number of bits in the displacement part of an address can address a block of only one half as many operands in double-word format as can be addressed in a single-word format.

This limitation on the number of double-word length operands in an addressable block is removed by using the displacement address part of the instruction for the variable address digits only and supplying the unchanging zero by logic circuits. Instruction register 1 of a processing unit receives an instruction word from instruction store 2. The instruction word comprises an operation code to instruct the processor and at least one operand address portion consisting of a base part and a displacement part. The base part of the address is passed to storage register group 3 to select the one containing the starting address, i.e., lowest, of the operand address block. The contents of the selected register 3 is passed to one input of adder 4. The displacement part of the address is passed through left shifter 5 into the other input of adder 4. Shifter 5 is controllabl...