Browse Prior Art Database

Counter Utilizing Pneumatic Hysteresis Latch

IP.com Disclosure Number: IPCOM000092290D
Original Publication Date: 1968-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Gunderson, PE: AUTHOR

Abstract

In drawing A, fluid-controlled apparatus utilizing flexible diaphragm control chambers performs a logic counting function. In drawing B, all elevated pressure levels are at supply pressure PS and all down levels represent ambient pressure PA.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 73% of the total text.

Page 1 of 2

Counter Utilizing Pneumatic Hysteresis Latch

In drawing A, fluid-controlled apparatus utilizing flexible diaphragm control chambers performs a logic counting function. In drawing B, all elevated pressure levels are at supply pressure PS and all down levels represent ambient pressure PA.

Prior to time equal zero, the fluid-operated devices are as shown in B which is the zero state of the counter. The set logic is gated to accept an input pulse at 12 and the reset logic is degated to reject an input pulse at 11. The first input pulse after time equal zero sets the hysteresis latch 15 to a logical 1 state causing the pulse at 10 to change from PA to PS. Since 13 causes a delay of longer duration than the input pulse, the set and reset logics do not change until the input pulse has returned to PA as shown at B in the first cycle.

When a pulse 10 has timed out through delay 13 the arrangement is ready to accept another input pulse. The input pulse is degated from the set logic by the pulse at 12 and the input pulse is gated to the reset logic by the pulse at 11. Therefore, the second cycle input pulse resets latch 15 to the logical 0 state as shown at B in cycle 2. Further, the Nor apparatus portion generates a carry pulse which serves as the input pulse to the next counter stage.

After the pulse at 10 has timed out through delay 13, a third pulse can occur which places latch 15 in a logical 1 state in the same manner as cycle 1. No carry is generated since the And fu...