Browse Prior Art Database

Main Storage Address Register Bypass Method

IP.com Disclosure Number: IPCOM000092296D
Original Publication Date: 1968-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Metz, TA: AUTHOR [+2]

Abstract

In a central processing unit, the address of data to be accessed must be present at the input drive circuits to main store prior to the machine cycle Select time at which the selected store drive lines are to be energized. In addition, the address must be present for a predetermined time interval thereafter. Typically, an address register receives and stores the address for the desired interval. However, in some instances, such as branching on register bits in processors having very short cycle times, a portion of the address is not available at Select time because of circuit delays. The problem can be obviated by avoiding part of the circuit delays in the data flow path of the branch address generating circuits.

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Main Storage Address Register Bypass Method

In a central processing unit, the address of data to be accessed must be present at the input drive circuits to main store prior to the machine cycle Select time at which the selected store drive lines are to be energized. In addition, the address must be present for a predetermined time interval thereafter. Typically, an address register receives and stores the address for the desired interval. However, in some instances, such as branching on register bits in processors having very short cycle times, a portion of the address is not available at Select time because of circuit delays. The problem can be obviated by avoiding part of the circuit delays in the data flow path of the branch address generating circuits.

Drawing A shows one solution to the problem, i.e., momentarily bypassing address register 1 with that portion of the address which is not available at Select time. Thus the address portion, determined by branch conditions and set into branch assembler 2, is applied to the appropriate inputs to 1 and is also applied directly to appropriate inputs to main storage drivers 3. The output of address assembler 4 sets the remaining portion of 1 sufficiently in advance of the Select time. With this arrangement, the time delay through 1 is not encountered by the address portion derived from 2, permitting energization of drivers 3 at Select time. The output of 2 sets the appropriate part of 1 prior to termination of the o...