Browse Prior Art Database

Multiply Divide

IP.com Disclosure Number: IPCOM000092298D
Original Publication Date: 1968-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 4 page(s) / 65K

Publishing Venue

IBM

Related People

Hanf, WP: AUTHOR

Abstract

Microprogram controls are provided to obtain higher speed binary multiply and divide operations in a microprogrammed processor and to reduce the burden of the programmer. These controls facilitate multiply-divide algorithms which make use of a one byte, 8 bits wide, ALU with the added ability to shift left one bit on the B input. In binary multiply, the left-shift ability permits the double of the multiplicand to be added into the partial product field. This halves the number of different multiples of the multiplicand that must be stored. In binary divide, the left-shift ability permits the dividend field to be shifted left simultaneously with the addition to or subtraction from the divisor. This halves the number of microinstructions executed in the main loop.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 32% of the total text.

Page 1 of 4

Multiply Divide

Microprogram controls are provided to obtain higher speed binary multiply and divide operations in a microprogrammed processor and to reduce the burden of the programmer. These controls facilitate multiply-divide algorithms which make use of a one byte, 8 bits wide, ALU with the added ability to shift left one bit on the B input. In binary multiply, the left-shift ability permits the double of the multiplicand to be added into the partial product field. This halves the number of different multiples of the multiplicand that must be stored. In binary divide, the left-shift ability permits the dividend field to be shifted left simultaneously with the addition to or subtraction from the divisor. This halves the number of microinstructions executed in the main loop.

In addition to the expanded arithmetic capability provided by this left-shift, controls are provided to aid the bookkeeping operations needed in the main loops of binary multiply and divide. The controls almost entirely eliminate the need for nonarithmetic words in the main loops. Thus, the adder is kept at work on the necessary adds and subtracts almost continually during the main loops. Rather than provide special branches to determine the operation to be done next and then provide the direct controls to accomplish the operations, indirect ALU controls are provided and based on the data bits and thus eliminate the need for most of the branching. This more direct hardware arrangement reduces the number of control combinations needed in the microwords and also reduces the number of microinstructions needed in the main loops.

The multiply algorithm which the hardware implements is as follows. The 1X, 4X, 16X, and 64X multiples of the four byte multiplicand are generated and kept in the high-speed local store 1. The 2X, 8X, 32X and 128X multiples of the multiplicand are generated by a shift left of the 1X, 4X, 16X and 64X multiples before entry into ALU 2. This eliminates the need to shift the partial product on less than byte boundaries.

The multiplier is processed two bits at a time starting with the low-order bits. Depending on the value of the two bits and whether or not the preceding multiplier bits call for an add or a subtract, the 1X, 4X, 16X, or 64X multiplicand or its double is added to or subtracted from the partial product. The determination of single or double and add or subtract is based on three bits, B0, B1, and B2, of the multiplier. B0 and B1 are the multiplier bits being processed and B2 is the higher order bit of the pair of bits last processed. The determination is according to the table shown at 3 in hardware controls 4.

One byte of the multiplier is held in T register 5 at a time and portions of it are selectively gated to assembler 6 whose output is the values of B0, B1, and B2. The high-order bit of the previous multiplier byte is loaded into S0 of S register 7. The bits gated to the assembler in sequence to form B0, B1, and B2 for eac...