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Resistance Mapping Comparator

IP.com Disclosure Number: IPCOM000092300D
Original Publication Date: 1968-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Ash, RJ: AUTHOR [+2]

Abstract

This resistance mapping comparator performs impedance measurements between any combination of circuit card tabs and the standard solder nodes on the back of the card. The test program data for a particular card is generated by testing a known good card and tabulating the results. The corresponding data obtained from testing a defective card is compared to the tabulated results for the good card to detect such faults as incorrect or damaged components or shorted or open lands. Test failure information for the defective card is then provided on a printed list in which the card tab and solder node coordinates for each failure are indicated. A node refers to all holes on a card that make up the point where either components or lands or both meet to form each particular type of card.

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Resistance Mapping Comparator

This resistance mapping comparator performs impedance measurements between any combination of circuit card tabs and the standard solder nodes on the back of the card. The test program data for a particular card is generated by testing a known good card and tabulating the results. The corresponding data obtained from testing a defective card is compared to the tabulated results for the good card to detect such faults as incorrect or damaged components or shorted or open lands. Test failure information for the defective card is then provided on a printed list in which the card tab and solder node coordinates for each failure are indicated. A node refers to all holes on a card that make up the point where either components or lands or both meet to form each particular type of card.

The system includes test socket 1 containing the necessary contacts to complete the circuits to the largest card to be tested. Controller 2 contains computer 10, program controlled matrix switch 3 as well as other interface circuitry such as resistance measuring device 4 and analog-to-digital converter 5. Also associated with the control unit is reader punch 6 used to load the main program into the controller storage. Disk file 7 provides auxiliary storage space for the part number program that is generated as a result of the test as well as other storage requirements. Typewriter 8 manually allows various modifications and corrections to the main program to accommodate special connections to the card that are required during a test. Typewriter 8 also functions to type out program error messages. Printer 9 provides the printed lists that locate the defective card sections according to their X-Y coordinates and other required data.

To detect malfunction of individual test probes in socket 1 that indicate a defective circuit, automatic devices are included to advance to another probe contacting the same network and then test prior to indicating that a particular circuit node is defective. To further minimize variations in the testing procedure that result in a rejection of good cards, the master card and the cards being tested utilize the same socket 1. The test made on the known good card is placed in storage to provide the data for comparison against each card being tested.

Four primary types of tests are performed to develop each particular card program. These tests include testing for used and unused nodes, network continuity tests, automatic current ranging, and network-to-network impedance measuring.

To activate the used-unused node test the reference card is placed in socket 1 and the main program is fed into controller 2 from reader punch 6. This program sets the proper controls in the control and interface circuits, selects the level detector voltage, selects the current value, and sets the interval timer. The node under test is connected to one input of the measurement circuit...