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Browse Prior Art Database

Interconnecting Monolithic Circuit Elements

IP.com Disclosure Number: IPCOM000092345D
Original Publication Date: 1967-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Ecker, ME: AUTHOR

Abstract

Transmission lines 10 are stacked with their edges perpendicular to the plane of monolithic chip 12 so as to increase the density of connections that can be made to such chip. An insulator 14 is clad on both sides with a conductive material so as to form signal line 16 on one side and ground plane 18 on the other side. Insulating layers 20 are provided between each transmission line 10. The lines 10 are stacked at right angles to each other so as to allow connections to be made all the way around the edge of chip 12. To allow the connections to be made, line 16 has a tab 22 which is bent so as to overlie ground plane 18 and is spaced from such ground plane by insulating block 24. This permits chip 12 to be mounted in a balls-down configuration on the array of transmission lines.

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Interconnecting Monolithic Circuit Elements

Transmission lines 10 are stacked with their edges perpendicular to the plane of monolithic chip 12 so as to increase the density of connections that can be made to such chip. An insulator 14 is clad on both sides with a conductive material so as to form signal line 16 on one side and ground plane 18 on the other side. Insulating layers 20 are provided between each transmission line 10. The lines 10 are stacked at right angles to each other so as to allow connections to be made all the way around the edge of chip 12. To allow the connections to be made, line 16 has a tab 22 which is bent so as to overlie ground plane 18 and is spaced from such ground plane by insulating block 24. This permits chip 12 to be mounted in a balls-down configuration on the array of transmission lines. The balls on the chip are connected to tabs 22 with solder reflow techniques.

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