Browse Prior Art Database

Time Shared Bus System

IP.com Disclosure Number: IPCOM000092356D
Original Publication Date: 1967-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Hiatt, GC: AUTHOR

Abstract

Data and storage addresses are transferred between channel 1 and memory server or bus control unit BCU over In Bus 2 having a bit width n less than bit width N of the information being transferred. To accomplish such transmission, the information is broken down into words each having n bits. The words are transmitted serially, by time-sharing, over bus 2.

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Time Shared Bus System

Data and storage addresses are transferred between channel 1 and memory server or bus control unit BCU over In Bus 2 having a bit width n less than bit width N of the information being transferred. To accomplish such transmission, the information is broken down into words each having n bits. The words are transmitted serially, by time-sharing, over bus 2.

The BCU has a series of registers R1...R3. These receive consecutive words through a series of gates G1...G3. Each register stores n bits and all registers store N bits.

In operation, a Request Storage Access signal actuates the channel causing it to place the first word of information on In Bus 2. The first word contains the address where the data is to be stored. At the same time, a Gating Signal is applied to G1 causing word 1 to be placed in R1 so that this register acts as a storage address register.

In a similar manner, words 2 and 3, containing the data to be stored are serially placed on In Bus 2 and then in R2 and R3 by Gating Signals applied to G2 and G3. The system can also be used to transmit addresses only and variable amounts of data by suitably controlling the placing of words on In Bus 2 and the gates. A similar bus system can be used to transmit information in the reverse direction from the BCU to channel 1.

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