Browse Prior Art Database

Chip Capacitor Configuration

IP.com Disclosure Number: IPCOM000092379D
Original Publication Date: 1967-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Miller, LF: AUTHOR [+2]

Abstract

In a multilevel ceramic chip capacitor, electrical contact to internal discrete conductive layers or planes is established by employment of via holes with conductive powder. The technique, as shown in A, involves forming a plurality of green ceramic sheets 11. Such forming is effected by separate dry pressing operations or cutting the plurality from flexible ceramic tapes, punching via holes 12 in sheets 11, and screening conductive layers 13 on the separate sheets such that they overlap holes 12 where contact is desired, as at 14, but are set back where it is not desired as at 15.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Chip Capacitor Configuration

In a multilevel ceramic chip capacitor, electrical contact to internal discrete conductive layers or planes is established by employment of via holes with conductive powder. The technique, as shown in A, involves forming a plurality of green ceramic sheets 11. Such forming is effected by separate dry pressing operations or cutting the plurality from flexible ceramic tapes, punching via holes 12 in sheets 11, and screening conductive layers 13 on the separate sheets such that they overlap holes 12 where contact is desired, as at 14, but are set back where it is not desired as at 15.

Then, as shown in B, the sheets are stacked in registry and laminated. Holes 12 are filled with conductive metal powder 16. The laminate is fired to cure the ceramic, sinter the powder, fire the paste forming the metal layers and bond them to the fused powder. A final immersion in solder 17 completes the capacitor configuration 18. Dielectric sheets 11 shrink during firing, squeezing the layers into contact with the powder 16, thus assuring good electrical connection. The conductive planes are sealed in by the dielectric and the tinned vias. Finally, the difficult edge metallization step is eliminated, thus also permitting a more flexible geometry.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]