Browse Prior Art Database

Memory Queueing Devices for Multiprocessor System

IP.com Disclosure Number: IPCOM000092428D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Lee, JM: AUTHOR [+2]

Abstract

The queueing system rapidly queues requests from a number of requestors, i.e., utilization devices, divided into a number of priority levels. The basic element of such system is the scanner.

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Memory Queueing Devices for Multiprocessor System

The queueing system rapidly queues requests from a number of requestors,
i.e., utilization devices, divided into a number of priority levels. The basic element of such system is the scanner.

When the responder, i.e., memory module, is ready to service the next requestor, the scanner determines which requestor is to be serviced next and signals acceptance to that requestor. The decision is made first on a priority basis and then on a cyclical scanning basis, which has some of the attributes of first-in-first-out queueing. This system is useful for computer storage modules servicing requests from data channels, processors, etc.

If the scanner is in its idle state in which no requests are currently present, any request signal that arrives sets the corresponding latch in the request registers. Logic 1 detects the left-most latch set in the case of simultaneously- arriving signals and sends this signal immediately to set the corresponding latches in the scanning register and the accept register. The latter sends an accept signal to the left-most requestor. The control unit signals the responder to commence servicing the request.

If the scanner is not idle, when the responder signals readiness to service the next request, the control unit causes the appropriate half of the scanning register to cycle under control of logic 2, looking for the first 1 bit in the request register. When this is found, the accept register is...