Browse Prior Art Database

Exponent Update and Latch in Three Levels

IP.com Disclosure Number: IPCOM000092432D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Litwak, M: AUTHOR [+3]

Abstract

Exponent updating for postnormalization of the results of a floating point addition with an exponent underflow and exponent overflow checking device as an integral part of high-order carry-out and with parity checking, normally utilizes at least four logic levels. This is required where a 7-bit exponent is updated.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Exponent Update and Latch in Three Levels

Exponent updating for postnormalization of the results of a floating point addition with an exponent underflow and exponent overflow checking device as an integral part of high-order carry-out and with parity checking, normally utilizes at least four logic levels. This is required where a 7-bit exponent is updated.

A 7-bit parallel adder with carry lookahead in the lower orders and group carry-out of the four lower orders into a carry lookahead in the three higher orders can be implemented in only three levels of logic. Such occurs if the three highest orders of one of the operands can be restricted to only 000 or 111.

For example, assume there are a 14-digit hexadecimal fraction word, with a 7-bit exponent to be updated, and a sign bit. After addition in adder 8, the sum, 14 digits plus a possible overflow, enters the leading zero detector 9. The exponent update amount is determined in detector 9 and is transmitted as a 7-bit number, up to binary 13 in complement form when subtraction is called for. It is transmitted in true form as a binary 1 for an addition of 1 to the exponent when the fraction has an overflow bit. The high-order bits 5, 6, and 7 of the updating amount are all 0's for a fraction overflow or for no leading 0's and are all 1's in all cases of subtraction. These bits are initially combined with the exponent bits 5, 6, and 7 in partial sum units PS5, PS6, and PS7. The four low-order addition bits are initially combined in partial sum units PS1, PS2, PS3, and PS4 wit...