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Memory Queueing System

IP.com Disclosure Number: IPCOM000092433D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Cocke, J: AUTHOR [+2]

Abstract

In many high-speed scientific computers the primary limiting factor on system speed is the time for a memory cycle. For example, a memory cycle can be of the order of five times greater than a machine cycle. In order to take advantage of this higher machine cycle speed, this system utilizes overlapping memories and, for the speed ratio just mentioned, at least five memories are needed. More than five is desirable. In addition to the overlapping memories, a queueing method is required. The queue permits the CPU to operate practically continuously without waiting for memory accesses.

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Memory Queueing System

In many high-speed scientific computers the primary limiting factor on system speed is the time for a memory cycle. For example, a memory cycle can be of the order of five times greater than a machine cycle. In order to take advantage of this higher machine cycle speed, this system utilizes overlapping memories and, for the speed ratio just mentioned, at least five memories are needed. More than five is desirable. In addition to the overlapping memories, a queueing method is required. The queue permits the CPU to operate practically continuously without waiting for memory accesses.

It is assumed that any memory M0...Mn can be started at the beginning of any machine cycle and, for the speed ratio chosen for this example, that the memory cycle extends through five machine cycles. Counter devices are provided which indicate which fifth of a memory cycle any busy memory is in such as the first fifth, the second fifth and so on, up to and including the fifth fifth. If a request is made for a particular memory in a certain machine cycle and it is known that this memory is busy and that it is in, for example, the second fifth of its cycle, then it is also known that if this request is delayed for three machine cycles that the memory can again be accessed. Such is provided that no other memory is scheduled to start its cycle at that time. There is only one output bus and because of this, only one memory can be started each machine cycle. If, during the machine cycle that the request is made it is known that the memory is to be free on the next machine cycle and that no other memory is to be started the next machine cycle, then the request can go directly from the input buffer to the memory. Such occurs by the path 10. Otherwise, the request goes into the queue.

The plurality of memories M0, M1...Mn is near the b...