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Automatic Calibration of a Recirculating Analog To Digital Converter

IP.com Disclosure Number: IPCOM000092441D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Schulz, RA: AUTHOR

Abstract

Upon command of a central processor, or the like, an A-to-D conversion is initiated by closing switch S1 to connect output terminal 11 of analog multiplexor 10 to comparator 12 of recirculating A-to-D converter 13. If comparator 12 determines that the analog input signal is less than a reference voltage, a zero digital signal is generated and switch S2 is operated to the minus full scale terminal 14 of voltage source 15. If the analog input signal is equal to or greater than the reference voltage, comparator 12 generates a binary one signal at the digital output and operates S2 to the plus full scale terminal 16 of voltage source 15.

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Automatic Calibration of a Recirculating Analog To Digital Converter

Upon command of a central processor, or the like, an A-to-D conversion is initiated by closing switch S1 to connect output terminal 11 of analog multiplexor 10 to comparator 12 of recirculating A-to-D converter 13. If comparator 12 determines that the analog input signal is less than a reference voltage, a zero digital signal is generated and switch S2 is operated to the minus full scale terminal 14 of voltage source 15. If the analog input signal is equal to or greater than the reference voltage, comparator 12 generates a binary one signal at the digital output and operates S2 to the plus full scale terminal 16 of voltage source
15.

Coincidentally with the reference comparison by comparator 12, the analog input signal is amplified by plus 2 by linear amplifier 17. The amplified signal is applied through delay line 18 to one side of subtract circuit 19. Delay 18 can be any device which is capable of delaying an analog signal. An alternate arrangement is a pair of sample and hold circuits operating with sample control signals which are 180 degrees out of phase or complementary. The other side of circuit 19 connects to the common terminal of S2. An output signal from circuit 19 representing the difference between the outputs of delay 18 and S2 is a new analog signal to be applied to comparator 12 when S1 is operated by the control processor to make contact with terminal 20. The difference signal from circuit 19 is now converted by comparator 12 to a binary zero or one to produce a second digital output signal. In addition, S2 is switched to minus full scale or plus full scale, as the case may be, and the second new analog signal is coincidentally passe through amplifier 17 and delay 18 to circuit 19. The process of recirculation by feedback from circuit 19 is repeated within converter 13 as many times as required to produce the predetermined number of digital signal bits to complete the conversion. At that time, S1 on command from the processing unit, is operated to switch to terminal 11 of multiplexor 10 and a subsequent analog input can be supplied to converter 13.

To correct for bias and gain errors caused by drift in converter 13, known analog inputs calibrate 1, calibrate 2, are periodically applied in succession through multiplexor 10 on command from the central processor. The calibration inputs are preferably +1/2 and -1/2 full scale voltage. Thus it is possible for each second bit of the digital output to become an indicator of the direction of the error. In each case, if the second bit is a binary zero, the digital output is too far negative, as shown by the line 21 on drawing B. If the second bit is binary one, then the digital output is assumed to be too far positive. Differences from the ideal characteristic, line 22, can be caused by either converter bias or converter ...