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Memory Write Error Detection

IP.com Disclosure Number: IPCOM000092470D
Original Publication Date: 1966-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Sellers, FF: AUTHOR

Abstract

This circuit provides an error check of magnetic core memory 10 into which data from write register 12 is written. The output of register 12 drives inhibit drivers 14 which drive memory array 10. The output of register 12 is also provided via bus 16 to a plurality of Exclusive-Or's 18. Data written into memory 10 is sensed during the write cycle by sense amplifier 20, the output of which sets the data into read data register 22. The outputs of register 22 drive the Exclusive-Or's 18 in conjunction with the outputs of register 12. When the data written into memory 10 properly switches the cores, the data read by amplifier 20 into register 22 is identical to that stored in register 12. Thus in an error-free operation the outputs of Exclusive-Or's 18 remain zero.

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Memory Write Error Detection

This circuit provides an error check of magnetic core memory 10 into which data from write register 12 is written. The output of register 12 drives inhibit drivers 14 which drive memory array 10. The output of register 12 is also provided via bus 16 to a plurality of Exclusive-Or's 18. Data written into memory 10 is sensed during the write cycle by sense amplifier 20, the output of which sets the data into read data register 22. The outputs of register 22 drive the Exclusive-Or's 18 in conjunction with the outputs of register 12. When the data written into memory 10 properly switches the cores, the data read by amplifier 20 into register 22 is identical to that stored in register 12. Thus in an error-free operation the outputs of Exclusive-Or's 18 remain zero. If any one of the outputs is not zero, an error has occurred and this output is transmitted through Or 24. The output of Or 24 is sampled at And 26 which provides an error output indication.

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